1. Field of Invention
The present invention relates to a sense amplifier circuit. More particularly, the present invention relates to a sense amplifier circuit that uses different routes to carry out pre-charging and sensing.
2. Description of Related Art
In general, sense amplifiers can be divided into two sections, a pre-sense circuit and a latch circuit. FIG. 1A is a circuit diagram of a conventional pre-sense circuit and FIG. 1B is a circuit diagram of a conventional latch circuit. To describe the operation of the sense amplifier circuit, a timing diagram of the signals used by the sense amplifier is shown in FIG. 3. In the pre-charge period, the signal PCB (the pre-charge signal) is pulled down and the output voltage VZ is pulled up via the transistor M4. In the meantime, because the signal SAB (sense amplifier enable signal) is pulled down, voltage at the data input terminal DL is pulled up to a high potential due to the simultaneous action of the transistors M2 and M5.
As the sense amplifier moves from the pre-charge period into the data-sensing period, the transistor M4 is shut down as voltage of the PCB signal is pulled up. At this moment, data is input into the pre-charge circuit 10 through the data line DL. If the data is a xe2x80x9c0xe2x80x9d (a high potential), the output voltage VZ is maintained at the original high voltage state. On the other hand, if the data is a xe2x80x9c1xe2x80x9d, (a low potential), current is dissipated via the transistor M5 and potential of the output voltage VZ is pulled down.
Finally, as the sense amplifier moves into the data-latching period, potential of the LATB signal (latch signal) is pulled up. Hence, the output voltage VZ provided by the pre-sense circuit 10 is applied to the latch circuit 14. The latching portion (consisting of inverters M10 and M11) of the latching circuit 14 latches the resultant signal from the phase-reversing portion (consisting of transistors M6-M9) of the latching circuit 14. After ascertaining the validity of the data, a SAB signal and a voltage source for driving subsequent circuit are output from the latching circuit 14.
In brief, to increase the sensing speed of the sense amplifier, time for pulling the voltage VZ from a high potential to a low potential must be shortened. A faster pull-down time may be achieved by (i) increasing the voltage gain of the NOR logic gate 102, (ii) lowering the parasitic loading of the output voltage VZ, or (iii) adding a diode between the transistor M4 and the power source voltage VDD. However, method (i) may lead to over-sensitivity of the sense amplifier to noise. For method (ii), because the output voltage VZ must have a definite degree of parasitic loading to prevent noise coupling, ultimate reduction in parasitic loading is limited. Although method (iii) is capable of reducing the degree of fluctuation of the output voltage VZ, the pre-charging operation is carried out at different voltages and temperatures, leading to unpredictable instability. Such instability may lead to insufficient or excessive pre-charging at the data input terminal DL, thereby affecting ultimate sensing accuracy.
Accordingly, one object of the present invention is to provide a sense amplifier circuit capable of increasing data-sensing speed with no accompanying drawbacks.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a sense amplifier circuit. Data is fed to a data input terminal of the sense amplifier and the sense amplifier operates according to a pre-charge signal, a latch signal and a sense amplifier enable signal. The sense amplifier circuit includes a pre-charge sense circuit capable of receiving data from a data input terminal and outputting a first output value. The sense amplifier circuit also includes a latching circuit capable of receiving the first output value and outputting a second output value after a preset period. The pre-charge sense circuit further includes a first circuit and a second circuit. The first circuit is capable of pre-charging the data input terminal to a preset potential level. The second circuit is capable of generating the first output value based on input data fed to the data input terminal. In addition, the first circuit and the second circuit are connected in parallel between a voltage source and a data input terminal.
This invention also provides a sense amplifier circuit for sensing data fed to its data input terminal and operates according to pre-charge signals, latching signals and sense amplifier enable signals. The sense circuit includes a plurality of transistors and a latching circuit. The first conductive terminal of a first transistor is electrically coupled to a voltage source and the gate terminal of the first transistor is electrically coupled to a pre-charge signal terminal. The second conductive terminal of a second transistor is electrically coupled to the data input terminal. A logic gate operation between the data input terminal signal and the sense amplifier enable signal is carried out by a NOR logic gate. Output from the NOR logic gate is fed to the gate terminal of the second transistor. The first conductive terminal of the second transistor and the second conductive terminal of the first transistor are electrically connected together. The first conductive terminal of a third transistor is electrically coupled to the voltage source and the second conductive terminal of the third transistor is electrically coupled to the gate terminal of the third transistor. The first conductive terminal of a fourth transistor is electrically coupled to the second conductive terminal of the third transistor and the gate terminal of the fourth transistor is electrically coupled to the pre-charge signal terminal. The first conductive terminal of a fifth transistor is electrically coupled to the second conductive terminal of the fourth transistor and the second conductive terminal of the fifth transistor is electrically coupled to the data input terminal. The result of the aforementioned logic computation is fed to the gate terminal of the fifth transistor. The latching circuit includes an input terminal and an output terminal. The input terminal of the latching circuit is electrically coupled to the second conductive terminal of the fourth transistor for receiving an output value. In addition, according to the latching signal, the output terminal of the latching circuit outputs an output value that corresponds to the received output value from the input terminal within a preset period.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.